In data communications, data is typically organized in structures such as packets which include multiple bits of data arranged in a predefined format. In transmission, it is common for data to be serialized and transmitted over a medium for reception at a remotely located receiver. At the receiver, in order to properly interpret the received data, it is necessary to reconstruct the received data in its original structure; e.g., if the data was originally organized in packets, it is necessary to delineate the original packet boundaries from the serialized data.
Frame delineation or alignment typically refers to a process or mechanism at the receive side of the network medium interface which realigns serially transmitted data into a known format and alignment for subsequent packet/frame or cell processing.
In some data communications systems, the individual bits of serialized data are recovered at the receiver using a clock derived from the serial data stream itself. Since the clock derived is dependent only on the “0” and “1” bit transitions, the recovered traffic need not be aligned to any position on the data path. Additional, synchronization information must be inserted into the serial data stream at the transmitter in order to mark or delineate packet or frame boundaries.
When performing packet or frame delineation, the probability that the synchronization information (e.g., “sync” bits, bytes, words) will be at an odd location with respect to the data path is the same as the probability that it will be at an even location. Due to the randomness of traffic from the network, a known approach has been to iteratively take a best guess at the position of the synchronization information and to prove or disprove the guess through repetitive checks. Prior art algorithms tend to stay on the odd or on the even guesses until all possibilities are exhausted. This approach may cause the acquisition time to be unnecessarily long.
In data communications, packet delineation functions are carried out by the Physical Coding Sub-layer (PCS). Components of this layer reside in both the transmitting and receiving ends of a communication. The PCS codes the data on transmission so that the alignment is recoverable on reception. At the transmitter, the PCS adds to each packet, at a fixed location within each packet, a pattern which the receiver looks for at reception.
In 10 Gb Ethernet for example, defined by IEEE Standard 802.3ae, the PCS packet delineation algorithm is referred to as “66b/64b .” In accordance with this algorithm, a two-bit sync pattern (or “sync header”) is inserted after every 64 bits of data. As such, for every 64 bits of data, 66 bits are transmitted. The 64b/66b algorithm replaces the 10b/8b algorithm used for Gigabit Ethernet (and below). This change was primarily motivated by the fact that a 25% overhead for this function was too costly at 10 Gb speeds which meant a loss of 2.5 Gb of bandwidth.
The implementation of a PCS algorithm involves a systematic transition among a synchronized state, an unsynchronized state, and a so-called “slip” state. The synchronized state is said to have been attained when a predetermined number of consecutive frames (e.g., 64) have been received correctly (i.e., with proper frame alignment). Synchronization is lost and the unsynchronized state is said to have been entered if a predetermined proportion of frames (e.g. 16 out of 64) are not received with proper frame alignment or the bit error rate (BER) exceeds a predetermined threshold. Once that occurs, the PCS algorithm will enter the slip state in which it attempts to acquire synchronization.
The duration of the slip state, which is indicative of the performance of the PCS algorithm, is typically sensitive to several considerations. A first consideration is the bias that the algorithm has as to whether the sync headers occur at even or odd positions (relative to some initial reference) within the serial data stream. An algorithm with an even bias will exhaust all of the even possibilities before considering any odd possibilities, whereas an algorithm with an odd bias will exhaust all of the odd possibilities before considering any even possibilities.
A second consideration is whether the algorithm looks for the sync header pattern only at a fixed position in the serial bit stream or whether it is capable of varying the position along the bit stream at which it will look for the sync header pattern. The former approach, which is typical of known implementations, further delays the acquisition of synchronization. This is because unless a hit occurs with the aligned position at the right time, several false sync positions may be taken, based on the pattern of data, until proven to be incorrect.
The present invention avoids the above discussed limitations of the prior art which contribute to delays in acquiring synchronization.